In the back end interconnect process of manufacturing a semiconductor device, it is necessary to establish electrical connection between a first layer of metal wiring and an active device structure at a lower level having both source/drain regions and a gate region. Accordingly, a local interconnect structure of the semiconductor device must be formed in advance before formation of the first layer of metal wiring. The local interconnect structure comprises contact through-holes for connecting the first layer of metal wiring with the source/drain regions or the gate region at a lower level. However, the contact through-holes at the source/drain regions and the gate region of the semiconductor device usually do not have the same length. For example, FIG. 1 illustrates contact through-holes formed between a first layer of metal wiring and source/drain regions or a gate region at a lower level in the prior art. As shown in FIG. 1, the contact through-holes 101, 103 at the source/drain regions and the contact through-holes 105, 107 at the gate regions of the semiconductor device are not in the same depth, which consequently makes it difficult to etch contact through-holes at different regions in a local interconnect structure and to deposit conductive materials.
Specifically, since the contact through-holes at the source/drain regions and the gate regions are not in the same depth, it is hard to control the time for stopping etching of the contact through-holes in the local interconnect structure. If the etching is stopped when the bottom of the contact through-hole at the gate region comes into contact with the gate, then the bottoms of the contact through-holes at the source/drain regions usually do not have a sufficient depth to be in contact with the source/drain regions. As a result, the bottoms of the contact through-holes at the source/drain regions will be separated from the source/drain regions by local interconnect dielectric, and thus may not be electrically connected with the source/drain regions. However, if the etching is stopped when the bottoms of the contact through-holes at the source/drain regions come into contact with the source/drain regions, then the bottom of the contact through-hole at the gate region shall extend into the gate, which would bring about over-etching of the gate and destroy integrity of the gate. Furthermore, it is likely to cause excessive gate leakage current in the gate dielectric layer below the gate, and thus cause unfavorable effects on controlling of switch for the semiconductor device.
Therefore, there is an urgent need for a method capable of forming contact through-holes at different regions in a local interconnect structure in back end local interconnect process for manufacturing a semiconductor device, and preventing over-etching of contact through-holes at gate regions (hereinafter referred to as gate through-holes) or under-etching of contact through-holes at source/drain regions (hereinafter referred to as source/drain through-holes).